(TO DO) Inventory of all the hardware of the Pixel Trigger
(DONE) Installation of full system at point 2
(DONE) Installation of power bus for side a in PIT crate with 6 power cables
(DONE) Install all Zarlink optical modules on the OPTIN boards
(DONE) Program Control FPGA and Processing FPGA of board V1, OPTIN boards (in DSF) with latest firmware (available on G:/Users/g/gaglieri/public/programming_files/)
(DONE) Verify that all channels on the OPTIN boards receive optical signals and lock onto the G-LINK coming from the MPT card runnign the MCM emulator
(DONE) Long term BER tests of the OPTIN boards
Memory access tests
*(DONE)*Fast-OR transmission tests with the MPT board/MCM emulator
(DONE) Insert OPTIN boards in the JTAG chain of BRAIN board by setting jumpers properly
(DONE) repair (substitution) of the faulty Agilent chip on the OPTIN board that is in the DSF installed on the V1 board
(DONE) verify correspondence between HS in the SPD control and HS in the PIT control. This can be done by setting test pulses on the chip of a given HS, sending internal triggers and counting Fast-OR seen by the pit counters