ECAL DIF Information

The Detector Interface forms the bridge between the Very Front-End (VFE) chips integrated in the detector slabs, and the DAQ system. The connection with the DAQ is established by a LDA-DIF link, running over AC-coupled LVDS differential pairs on standard HDMI cables and connectors.

The HDMI connector on the EDIF has the following pinout:

NOTE that power is supplied on pins13 and 14, with accompanying GND on 18,19, by the DIF. Historically these pins were reserved to power external hardware for driving the LDA-DIF link if necessary. They should be Not Connected at the LDA end.

The DIF is connected with the slab, or, the intermediate board at the end of the slab, by a 90 pin connector of the following type:

• DIF: SAMTEC FSH of the 145-04-L-DH-SL
• Slab: SAMTEC SFMH 145-02-L-D-LC

Dif prototype (version 1)

ECAL DIF v1

Explanation of the DIF components indicated in the picture above:

1. JTAG programming header
2. HDMI connector for LDA-DIF link
3. DIF-DIF link connector
4. Mini-USB connector
5. PROM for Xilinx FPGA
6. Cypress SDRAM 2MB, 10ns
7. FPGA Xilinx Spartan3-1000
8. USB interface chip
9. User connector header
10. FPGA reload pushbutton
11. 90pin DIF-Intermediate board or Slab connector

For this DIF prototype, it was assumed that all power regulation hardware is located at the end of the slab, or, alternatively, on a intermediate board between the DIF and the slab. Therefore, power is supplied through the designated pins on the 90 pin interface connector. The User Constraints File for the DIF FPGA can be found here

Dif production prototype (version 2)

ECAL DIF v2 on a standard sized card

Schematics of the DIF version 2 can be found here, with the schematics for the ac-coupling of LDVS pairs here

The ECAL DIF v2 has regulators to generate 2V5 and 1V2 from the 3V3 supply. the jumper settings on J3 and J4 determine whether the on-board regulators are used to supply the DIF. Note that when the regulators are active, the voltages will also appear on the slab connector. Power is supplied through the power connector at the bottom left in the picture, or through the slab connector, similar to DIF v1.

EDIF Firmware for throughput tests

Hardware list

DIF ID	location	Comments
01	Cambridge	batch proto, tested OK
02	Cambridge	batch proto, tested OK
03	LLR @test1
04	LLR @test1
05	LLR @test1
06
07	LLR @test1
08
09
10
11
12
13
14	LLR @test1
15	LLR @test1
16	LLR @test1
17	LLR @remi	FAIL
18
19
20
21
22
23	LLR @test0	SLAB #1 4xspiroc2A
24	LLR @test1
25	LLR @test1
26	LLR @test1
27	LLR @test1
28	LLR @test1
29	LLR @test1
30	LLR @test1
31	LLR stoc
32	LLR @test0	SLAB #3 4*spiroc2 + wafer
33	LLR stoc
34	LLR @test0	SLAB #2 1*spiroc2 +wafer
35	LLR stoc
36	LLR stoc
37	LLR stoc
38	LLR stoc
39	LLR stoc
40	LLR stoc

-- BartHommels - 04-Mar-2010 -- RemiCornat - 08-Nov-2011