Status: Working. Other implementations have been tried, using BUFE and BUFT primitives but resulted in poorer performance. This method allows the data register to be migrated up the mux tree to achieve the required timing. If achieving the timing does become an issue in the future then an additional register stage can be added and the latency increased for that read (see PCIeInterface).
Description: This selects which register data is presented to the PCIe when a read is done.